1. Field of the Invention
This invention broadly relates to computer systems, and more particularly, to processor power management within a computer system where the processor is at one end of a clock forwarded interface.
2. Description of the Related Art
A computer system typically includes at least one processor (also referred to as a xe2x80x9cmicroprocessorxe2x80x9d) that typically performs processing of a number of instructions from one or more programs or applications under execution. As part of its processing operations, the processor may need to access a number of system buses for required data transfer. For example, a multimedia application may require the processor to transfer certain data to a separate video processor and retrieve the processed information from the video processor through a dedicated video bus. Further, the processor may communicate with one or more I/O devices through a separate I/O bus, and with one or more system memories through a dedicated memory bus. Additional buses may be present in the computer system based on the system device complexity and the level of interconnection among various electronic devices constituting the computer system.
The computer system may also include a bus bridge to effectively manage the binary information traffic between the processor and one or more system buses. The bus bridge may also facilitate cache coherent data transfers within the system in view of the possibility of independent memory accesses by the processor and one or more I/O devices. Various system components may be coupled to the processor via the bus bridge. In other words, the bus bridge may be directly connected to the processor, and, hence, may directly receive all address and data information from the processor. The bus bridge may, in turn, distribute the received information to appropriate system devices via appropriate system buses. Similarly, information received from one or more system devices over different system buses may be routed to the processor via the bus bridge in a systematic manner.
The bus bridge may be connected to the processor via a clock forwarded interface for high bandwidth data transfers. A clock forwarded interface accomplishes point-to-point transfers of binary information by having the sender provide the receiver with a forward clock that latches the transmitted data at the receiver. The receiver may then sample the received binary information using its internal clock. The address and/or data transmitted by the sender is synchronized to the forward clock by the sender. The clock forwarded interface thus requires the processor and the bus bridge to begin sending forward clocks in a deterministic manner. Further, the forward clocks from the processor and the bus bridge may be of equal frequency to provide consistent reference points during binary information transfers between them.
The processor is a typical semiconductor device that dissipates electrical power (i.e., transforms electrical energy into heat energy) during operation. At the same time, several key operating parameters of a semiconductor electronic device vary with temperature, and reliable device operation within specifications occurs only within a defined operating temperature range. For example, the specified performance of the processor is typically achieved only when the temperature of the processor is maintained below a specified maximum operating temperature. Operation of the processor at a temperature above the maximum operating temperature may result in irreversible damage to the processor""s internal circuitry. In addition, it has been established that the reliability of semiconductor electronic devices decreases with increasing operating temperature.
The electrical power dissipated by the processor directly depends, among other factors, on the speed (or frequency) at which the processor operates during run-time. The higher the operating frequency of the processor, the greater the generation of heat energy by the processor. However, the processor itself may be idle at various times during the length of program execution. For example, the processor may be waiting to receive a large stream of data from a video processor through the bus bridge, and the processor may not continue further program execution until it receives the requested data. In such an event, it may be desirable to place the idle processor into a low power consuming state by reducing the frequency of its internal clock. Operating the processor at its full internal frequency may not be desirable when the processor is idle.
In a clock forwarded interface, it is desirable that the processor not drive its forward clock to the bus bridge when the processor is in a low power state. It may therefore be desirable to allow the processor to enter and exit its low power state while also ensuring the requisite synchronism between the forward clocks from the processor and the bus bridge when the processor and the bus bridge are connected through a clock forwarded interface.
The problems outlined above may in large part be solved by a computer system as described herein. The computer system comprises a processor that is connected to a bus bridge via an interface bus, which, preferably, provides a clock forwarded interface between the processor and the bus bridge. The bus bridge, in turn, connects the processor to one or more system buses within the computer system. The bus bridge is configured to coordinate disconnection of the processor from the interface bus upon receiving from the processor an indication of such disconnection. The processor may be disconnected from the interface bus when the processor is idle.
In one embodiment, the computer system may further comprise an I/O bridge connected to the bus bridge via one of the system buses. The I/O bridge may further be connected to an I/O interrupt controller through an I/O bus to manage the interrupt traffic within the system as well as to provide an interface between the processor and one or more I/O devices within the system. In one embodiment, the I/O bridge provides a number of interrupt signals directly to the processor via corresponding pins directly connecting the processor and the I/O bridge.
The interface bus may include a CONNECT line, a PROCREADY line, a CLKFWDRESET line, and other data and address lines. The CONNECT and the CLKFWDRESET lines are sourced by the bus bridge, whereas the PROCREADY line is sourced by the processor. In one embodiment, the processor gets connected to the interface bus when both the CONNECT and the PROCREADY signals are asserted. The processor remains connected to the interface bus despite deassertion of one of these two signals. However, the processor may get disconnected from the interface bus when both the CONNECT and the PROCREADY signals are deasserted. The processor remains disconnected so long as both of these signals are not asserted.
Generally, the CONNECT and the PROCREADY signals are used to provide an orderly disconnection of the processor from the bus interface. Various transactions which are initiated in the computer system may require multiple communications across the interface bus. It is therefore desirable to complete outstanding transactions prior to disconnecting the processor from the bus interface.
In one embodiment, the processor may receive an indication of its disconnection from the interface bus when the I/O bridge asserts the STPCLK_L line or when the processor executes a HALT instruction. With the PROCREADY and the CONNECT lines still asserted, the processor""s microcode may mask the CONNECT line recognition until the processor""s bus interface unit becomes free. Thereafter, the bus bridge may first deassert the CONNECT line after verifying that no probes to the processor are pending in the system. The processor may then responsively deassert the PROCREADY signal unless the processor is to remain connected to the interface bus to complete one or more transactions. In that event, the processor issues a connect special cycle command to the bus bridge, which, in turn, reasserts the CONNECT signal until the desired transactions are completed.
After the deassertion of the PROCREADY signal, the bus bridge asserts the CLKFWDRESET signal. In one embodiment, the assertion of the CLKFWDRESET signal results in resetting of the clock forwarded interface. In other words, the processor and the bus bridge both stop their respective forward clocks and clear their respective clock forwarded data/address FIFOs. The processor may then ramp down its internal clock to a low frequency (i.e., the processor may enter its xe2x80x9casleepxe2x80x9d state) to save power. The processor may remain disconnected from the interface bus when asleep, and may remain in this disconnected state until reconnected to the interface bus. Additional power may be conserved due to the reset of the clock forwarded interface (since the forward clocks are not toggling).
The processor may be reconnected to the interface bus when it is xe2x80x9cawakexe2x80x9d, i.e., when the processor clock is running at its full frequency. The reconnection of the processor to the interface bus may depend on how the processor was earlier disconnected. The reconnection may be permanent or temporary. For example, in one embodiment, a deassertion of the STPCLK_L line may initiate a permanent reconnection of the processor in the event that the processor was earlier disconnected by the assertion of the STPCLK_L signal. Similarly, one or more of a number of interrupt signals from the I/O bridge may also permanently reconnect the processor in the event that the processor was put to sleep by the execution of the HALT instruction. However, the bus bridge may make the processor temporarily reconnect to the interface bus if the bus bridge needs to send a probe to the processor. The processor may also get temporarily reconnected to the interface bus upon assertion of the STPCLK_L signal while in the disconnected state through the execution of the HALT instruction.
As part of the reconnection, the processor ramps up its internal clock to its full frequency and asserts the PROCREADY signal. The bus bridge, in response, asserts the CONNECT signal and deasserts the CLKFWDRESET line. This causes the system forward clocks to begin and either party (the bus bridge or the processor) may begin the data transfer activity. The synchronism between the forward clocks from the processor and the bus bridge is thus maintained during disconnection and reconnection of the processor to the interface bus. Power conservation is also achieved by placing the idle processor in a low frequency state and by stopping the forward clocks.